Module simd32

Available on ARM only.

References

• Section 8.5 “32-bit SIMD intrinsics” of ACLE

Intrinsics that could live here

• [x] __sel
• [ ] __ssat16
• [ ] __usat16
• [ ] __sxtab16
• [ ] __sxtb16
• [ ] __uxtab16
• [ ] __uxtb16
• [x] __qadd8
• [x] __qsub8
• [x] __sadd8
• [x] __shadd8
• [x] __shsub8
• [x] __ssub8
• [ ] __uadd8
• [ ] __uhadd8
• [ ] __uhsub8
• [ ] __uqadd8
• [ ] __uqsub8
• [x] __usub8
• [x] __usad8
• [x] __usada8
• [x] __qadd16
• [x] __qasx
• [x] __qsax
• [x] __qsub16
• [x] __sadd16
• [x] __sasx
• [x] __shadd16
• [ ] __shasx
• [ ] __shsax
• [x] __shsub16
• [ ] __ssax
• [ ] __ssub16
• [ ] __uadd16
• [ ] __uasx
• [ ] __uhadd16
• [ ] __uhasx
• [ ] __uhsax
• [ ] __uhsub16
• [ ] __uqadd16
• [ ] __uqasx
• [x] __uqsax
• [ ] __uqsub16
• [ ] __usax
• [ ] __usub16
• [x] __smlad
• [ ] __smladx
• [ ] __smlald
• [ ] __smlaldx
• [x] __smlsd
• [ ] __smlsdx
• [ ] __smlsld
• [ ] __smlsldx
• [x] __smuad
• [x] __smuadx
• [x] __smusd
• [x] __smusdx

Macros

dsp_call 🔒

Functions

arm_qadd8 🔒 ^⚠

arm_qadd16 🔒 ^⚠

arm_qasx 🔒 ^⚠

arm_qsax 🔒 ^⚠

arm_qsub8 🔒 ^⚠

arm_qsub16 🔒 ^⚠

arm_sadd8 🔒 ^⚠

arm_sadd16 🔒 ^⚠

arm_sasx 🔒 ^⚠

arm_sel 🔒 ^⚠

arm_shadd8 🔒 ^⚠

arm_shadd16 🔒 ^⚠

arm_shsub8 🔒 ^⚠

arm_shsub16 🔒 ^⚠

arm_smlad 🔒 ^⚠

arm_smlsd 🔒 ^⚠

arm_smuad 🔒 ^⚠

arm_smuadx 🔒 ^⚠

arm_smusd 🔒 ^⚠

arm_smusdx 🔒 ^⚠

arm_ssub8 🔒 ^⚠

arm_usad8 🔒 ^⚠

arm_usub8 🔒 ^⚠

__qadd8^⚠Experimental

Saturating four 8-bit integer additions

__qadd16^⚠Experimental

Saturating two 16-bit integer additions

__qasx^⚠Experimental

Returns the 16-bit signed saturated equivalent of

__qsax^⚠Experimental

Returns the 16-bit signed saturated equivalent of

__qsub8^⚠Experimental

Saturating two 8-bit integer subtraction

__qsub16^⚠Experimental

Saturating two 16-bit integer subtraction

__sadd8^⚠Experimental

Returns the 8-bit signed saturated equivalent of

__sadd16^⚠Experimental

Returns the 16-bit signed saturated equivalent of

__sasx^⚠Experimental

Returns the 16-bit signed equivalent of

__sel^⚠Experimental

Select bytes from each operand according to APSR GE flags

__shadd8^⚠Experimental

Signed halving parallel byte-wise addition.

__shadd16^⚠Experimental

Signed halving parallel halfword-wise addition.

__shsub8^⚠Experimental

Signed halving parallel byte-wise subtraction.

__shsub16^⚠Experimental

Signed halving parallel halfword-wise subtraction.

__smlad^⚠Experimental

Dual 16-bit Signed Multiply with Addition of products and 32-bit accumulation.

__smlsd^⚠Experimental

Dual 16-bit Signed Multiply with Subtraction of products and 32-bit accumulation and overflow detection.

__smuad^⚠Experimental

Signed Dual Multiply Add.

__smuadx^⚠Experimental

Signed Dual Multiply Add Reversed.

__smusd^⚠Experimental

Signed Dual Multiply Subtract.

__smusdx^⚠Experimental

Signed Dual Multiply Subtract Reversed.

__ssub8^⚠Experimental

Inserts a SSUB8 instruction.

__usad8^⚠Experimental

Sum of 8-bit absolute differences.

__usada8^⚠Experimental

Sum of 8-bit absolute differences and constant.

__usub8^⚠Experimental

Inserts a USUB8 instruction.

Type Aliases

int8x4_tExperimental

ARM-specific vector of four packed i8 packed into a 32-bit integer.

int16x2_tExperimental

ARM-specific vector of two packed i16 packed into a 32-bit integer.

uint8x4_tExperimental

ARM-specific vector of four packed u8 packed into a 32-bit integer.

uint16x2_tExperimental

ARM-specific vector of two packed u16 packed into a 32-bit integer.